The power used by a CMOS integrated circuit comprises two main components: static power and dynamic power. Static power essentially consists of the power used when transistors are not in the process of switching. Static power consumption has been an increasing challenge for the semiconductor industry in recent years, with the increasing demand for longer life and a trend towards more environmentally friendly applications, combined with advances in manufacturing technology and miniaturization of components that has led to decreases in gate oxide thicknesses resulting in larger leakage currents.
A common technique used presently for reducing static power consumption is the powering down of internal components inside a semiconductor device when not required/used based on various algorithms typically implemented within upper layer software. A problem faced by these algorithms is that, because they are implemented within upper layer software, they are detached from the actual hardware activity, and cannot accurately predict the relevant hardware to power down. Accordingly, such algorithms are required to take a cautious approach to powering down components.